For a number of reasons, increasing device density in semiconductor devices requires the use of photoresist having a reduced thickness. Since resist may be too thin to use for patterning directly, hard mask materials such as TERA (Tunable Etch-Resistant ARC, where ARC stands for Anti-Reflection Coating) have been developed to enable patterning. The photoresist is used only to image a thin hardmask material, which subsequently serves as a pattern transfer mask for underlying films (e.g. silicon dioxide, silicon nitride and the like). TERA hard mask layers can in some applications provide simultaneous hard mask and ARC functionality.
TERA materials are defined as R—C—H—X, where R is selected from Si, Ge, B, and Sn; X is selected from O, N, S, and F; C is carbon, and H is hydrogen. The ranges include R from 0-95%, C from 0-95%, H from 0-50%, and X from 0-70% (by atomic percent). TERA materials are disclosed in U.S. Pat. No. 6,316,167 and U.S. Pat. No. 5,926,740, the disclosures of which are hereby incorporated by reference.
TERA is a desirable hard mask material because it has a low sputter yield (and hence is an effective mask material) in plasma etches for silicon dioxide (e.g. fluorine-based etch plasmas). Specifically, the TERA film commonly used as a hard mask for silicon dioxide contains a high level of carbon (e.g. about 20%). In many instances, it is necessary to open a composite stack comprising TERA, silicon dioxide, and silicon nitride below the oxide. Optionally, silicon under the nitride may be etched as well. Fluorocarbon based etching chemistry is preferred for etching the oxide and nitride. Hence, using a fluorocarbon-based or fluorine-compatible etching chemistry to strip the TERA layer after oxide etching would simplify processing. It would be most preferable to strip the TERA layer in situ after it has been used as a hard mask.
Since TERA is resistant to fluorine-based plasma etches, it is difficult to strip in situ when fluorine based processing is used. In particular, semiconductor manufacturers are currently experiencing difficulty in stripping TERA mask materials without also damaging underlying layers. Typically, stripping the TERA layer requires removing the wafer from the fluorine system and stripping the TERA in a chlorine based system. This increases the cost and complexity of using TERA hard mask/ARC layers, which are otherwise highly desirable. TERA materials can also be etched simultaneously with the nitride etch, but this approach causes other problems. Specifically, sidewalls in the nitride layer can become sloped, which can be undesirable for certain devices. This is primarily due to the additional C and Si load of the residual mask on the nitride etch process.
It is not practical to strip the TERA material with the same process used to pattern it from the resist mask because this unfavorably alters the profile of the oxide etch. Therefore, in the state of the art, there appears to be no simple, practical method for stripping TERA materials in a processing system employing fluorine chemistry.
It would be an advance in the art of semiconductor processing, and would facilitate the application of smaller feature sizes in semiconductor devices, to provide a method for stripping TERA materials in a fluorine based etching system. It would be particularly useful to provide a TERA strip method that does not unfavorably alter the profiles of underlying oxide or nitride films.